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qcom-clk-for-6.4
32c2f2a4 · ·Qualcomm Clock updates for v6.4 New drivers for Global clock controller on SM7150, IPQ9574, MSM8917 and IPQ5332 are added. New GPU clock controllers for SM6115, SM6125, SM6375 and SA8775P are added. The APSS IPQ PLL driver is refactored to support different PLL types, support for the Stromer Plus PLL type is added, and support for IPQ5332 is introduced. Helpers for settings sleep, wake and retain bits of CBCR registers are introduced and used in some of the newly introduced GPU clock drivers. platform_driver remove callbacks is transitioned to remove_new, as part of the system wide cleanup effort. In the Display clock controller for QCM2290, the MDSS_CORE reset is introduced and the non-existent DSI1PHY clock is removed. IPQ4019 Global clock controller is transitioned to parent_data. USB GDSCs in SM6375, MSM8996 and MSM8998 are changed to use retention as disabled state, to avoid collapsing them during suspend. The CX GDSC in the SM6375 GPU clock controller has it's disable-wait value corrected. QCM2290 SDCC2 src clock moves to floor_ops. The two EMAC GDSCs are added for SC8280XP. Relevant RCGs in the SM6115 Global clock controller are moved to use shared_ops. PCIe PIPE clock operations on SM8350 are updated, to ensure the mux is parked when the parent PLL is disabled. GDSCs are added to the SC7280 LPASS audio clock controller. The RPM clock controller is transitioned to use the managed version of of_clk_add_hw_provider(). Missing XO clocks are added to MSM8226 and MSM8974. DeviceTree bindings are added for the various newly supported clock controllers, the binding for KPSS ACC and GCC drivers are converted to YAML and a few fixes are introduced.
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