H

HDL

Hog (HDL-on-git) is a set of Tcl/Shell scripts plus a suitable methodology to handle HDL designs in a git repository. For more information, visit our documentation page: https://cern.ch/hog, or register to our newsletter: http://cern.ch/go/nBn8

A better hardware description language.

A library to represent and manipulate Hardware Description Language (HDL) block designs in Python

https://hdl-block-design.readthedocs.io/en/latest/

Python Register InterFace Translation

The pytest-fusesoc plugin allows to use pytest to discover and run simulation targets defined in FuseSoC *.core files. Furthermore, test capabilities can be greatly increased with existing pytest plugins, pytest built-in features like fixtures, test parametrization @pytest.mark.parametrize, tests reporting and more.

PyTCL allows control EDA tools directly from Python that use TCL.

CMake scripts for building FPGA/ASIC projects.

Wrapper for FPGA toolchain tools

Welcome to the repository for the VALE8x64 project.